The present invention relates to an integral-type A/D or D/A converter.
As an example of A/D converters, there has been known the integral-type A/D converter. In this integral-type A/D converter, an analog input signal is fed via a sampling switchelement to an integrator which consists of an operational amplifier and a capacitor. At the moment when the switch element is closed, the capacitor starts charging to the input voltage. The capacitor is connected with two constant current sources providing different supply currents through respective switches. At a time point when the sampling switch element is opened, the constant current sources have their switches closed, and the capacitor is discharged by the constant current sources. The two constant current sources provide currents I.sub.o and i.sub.o, which are set in magnitude to be, for example, I.sub.o :i.sub.o 2.sup.7 :1 or 128:1. Initially, the switch associated with the source of current I.sub.o is closed, causing the capacitor to start discharging, and the discharging time length until the capacitor voltage becomes the predetermined value is measured by an upper-bits counter. Subsequently, the switch associated with the source of current I.sub.o is opened and at the same time the switch associated with the source of current i.sub.o is closed, and the capacitor continues discharging until its voltage falls to zero volts, and the discharging time length is measured by a lower-bits counter. The count values left in the upper and lower bits counters in combination represent a 16-bit digital value as a result of A/D conversion for the input analog signal. The foregoing A/D converter is described in U.S. patent application Ser. No. 556,710 (filed on Nov. 25, 1983) by the applicant of the present invention, and a D/A converter using the same principle is described in U.S. Pat. No. 4,404,546 and U.S. patent application Ser. No. 432,845 (filed on Oct. 5, 1982).
The foregoing conventional A/D converter operates at a conversion speed which is determined from the length of time after the upper 9-bit counter has started counting until the lower 7-bit counter ends the count operation. The upper 9-bit counter has a count capacity of 2.sup.9 (i.e., 512), while the lower 7-bit counter has a count capacity of 2.sup.7 (i.e., 128). Accordingly, the total count capacity of the upper 9-bit counter and lower 7-bit counter is 640. For a given sampling frequency of 48 kHz, for example, 640 counts must be completed in each sampling period. If it is intended to implement A/D conversion for two channels alternately on a time division basis, the clock generator needs to produce a master clock at a frequency: fm.sub.1 =2ch.times.48 kHz.times.640=61.44 MHz.
In quantizing an input analog audio signal at a sampling frequency fs, it is necessary to confine the input analog signal within the band of fs using an analog low-pass filter in order to suppress the foldover (aliasing) noise created with the center at the sampling frequency fs. To achieve satisfactory characteristics up to a higher frequency region, the low-pass filter needs to have a sharp response curve, which, however, is difficult to realize using an analog low-pass filter.
In quantizing an input analog audio signal in a digital audio tape recorder, for example, a conceivable scheme is that the input signal is confined in a band of fs using an analog low-pass filter and, after it has been quantized at a doubled sampling frequency 2fs, it is finally confined in a band of fs using a digital filter. Namely, through the quantization process at a frequency twice the sampling frequency fs, quantization up to the band of fs is made possible based on the sampling theory. Since the band necessary for the sampling at frequency fs is up to a fs frequency, the use of a sharp digital low-pass filter tuned to the fs frequency eliminates the need of a sharp response for the analog low pass filter. A digital filter having a sharp response is more readily realized than an analog filter. On this account, through the quantization at a 2fs frequency and band limitation using a digital filter, satisfactory operating characteristics up to a high frequency region can be accomplished at a low cost.
In the above case of quantizing an input analog signal at a frequency twice the sampling frequency fs, the A/D converter needs to operate at a speed twice as fast as the case of quantization at the frequency fs.
For carrying out A/D conversion at a 2fs frequency which is twice as high as the sampling frequency fs using the foregoing conventional A/D converter, the master clock frequency fm required is doubled to 2.times.2ch.times.48 kHz.times.640=122.88 MHz. The master clock generator uses a crystal resonator, but it is difficult to have a stable master clock oscillation at such a high frequency using a crystal resonator.